1. Technical Field
This disclosure relates to analog-to-digital converters and more particularly to an integrated analog-to-digital converter having an improved accuracy and a reduced silicon area occupation, particularly suited for PSI5 and WSS (Wheel Speed Sensor) systems, and a related interface for PSI5 and WSS systems.
2. Discussion of the Related Art
Analog-to-digital converters are electronic devices even more frequently used in the automotive field for realizing interfaces of analog sensors installed in vehicles to a central control unit. In particular, the so-called PSI5 (Peripheral Sensor Interface) is even more used, for example, in combination with airbag sensors, and are characterized by limited costs, high speed and reliability of the data transfer and low overhead.
A typical example of a control system made of sensors connected to an electronic control unit (ECU) having a PSI5 interface is depicted in FIG. 1. The communication channel between the sensors and the electronic control unit of a PSI5 system may be basically represented as shown in FIG. 2. A typical electric diagram of a PSI5 or WSS (Wheel Speed Sensor) sensor and of the connection bus to the demodulator and decoder is shown in FIG. 3.
Nowadays, the most effective solution for processing a received analog signal consists substantially in converting the analog signal into a digital signal and in carrying out a demodulation of the digital data such to obtain a bit sequence adapted to be processed directly by a controller or a microprocessor for implementing a desired control action.
Downstream from the analog-to-digital converter, at least an anti-aliasing filter is typically provided for canceling conversion noise, such to prevent it from disturbing the demodulated noise. In PSI5 or WSS (Wheel Speed Sensor) systems, it is desirable to carry out fast analog-to-digital conversions and the successive low-pass filtering and to make these operations relatively robust against noise.
An analog-to-digital conversion loop has a feedback line including a digital-to-analog converter that provides an analog replica of the generated digital signal. Because of design constraints of the above mentioned systems, it is particularly important to realize this feedback loop such to obtain an output that goes quickly to the desired level corresponding to the time-varying analog input signal.
U.S. Pat. No. 6,229,469 shows an analog-to-digital conversion loop, shown in FIG. 4, wherein the input analog signal to be converted is compared with an analog amplified replica of the digital output signal. The difference between the two analog signals, that constitutes an output correction (increase or decrease) signal, is amplified and converted by a linear flash analog-to-digital converter, that generates increment or decrement digital values of an up or down counter, that on its turn generates the digital output corresponding to the analog input signal. The up/down counter practically carries out a low-pass filtering because in the digital domain its function substantially is that of a digital integrator, that reduces noise on the digital output.
A limitation of this analog-to-digital conversion loop consists in that it needs a sample and hold circuit in order to function correctly in presence of large variations of the input signal. Moreover, the used flash analog-to-digital converter is linear. Therefore, its architecture is as shown in FIG. 5, that requires a silicon area that increase with an exponential law with the number N of bits, and thus with the accuracy, of the output digital word DOUT.
The sample and hold circuit is needed in this architecture because it holds the analog error signal for the time necessary to allow the propagation thereof throughout the comparators, the encoder and the output buffer. If the sample and hold circuit were removed, then, in presence of a time varying input signal, the output buffer would upload a digital datum while the input is changing, thus causing errors that may be relevant.
Another known solution is depicted in FIG. 6 and is disclosed on the web-page www.echoescan.com/Predictor.htm. It is characterized by the presence in the digital domain on the feedback line of an error prediction filter. The output of this analog-to-digital conversion loop is high-pass and needs an amplifier GAIN and an analog-to-digital converter ADC inserted in the direct path with restrictive constraints of accuracy, because the accuracy may greatly influence the characteristics of the output signal.
U.S. Pat. No. 6,100,834 discloses an analog-to-digital conversion loop, shown in FIG. 7, wherein an adder 100 generates a correction signal given by the difference between an analog input signal to be converted Vin and an analog feedback signal corresponding to the digital output OUT. A high-pass filter generates a filtered replica S1 of the correction signal, that is thus converted in the digital domain by a flash linear analog-to-digital converter.
A drawback of this analog-to-digital conversion loop consists in the presence of the high-pass filter, that is relatively complex to realize. Moreover, the flash analog-to-digital converter should be particularly fast to generate an accurate digital replica of the high-pass signal S1, otherwise the depicted conversion loop would not function correctly because it does not have the sample and hold circuit, necessary for keeping constant the input of the converter for the time necessary to carry out the conversion.
FIGS. 8a and 8b depict known current sensing architectures of PSI5 and WSS sensors, that have a threshold-based discrimination system. They substantially compare a current ISat/100, that represents an analog quantity to be converted, with a threshold current determined by a logic circuit able to define the range to which the current belongs.
The architecture of FIG. 8a has a digital-to-analog feedback loop that allows tracking the average current of a PSI5 bus; a control logic is adapted to determine whether the instantaneous current through the bus exceeds or not a fixed threshold summed to the above average current. This allows locating the modulation edges. The scheme of FIG. 8b implements a digital-to-analog feedback loop that is able to discriminate, by means of three fixed additive thresholds, to which of the ranges of interest the instantaneous current of the bus belongs, thus allowing decoding of the modulation.
Even if the depicted circuits have a relatively fast transient response, they occupy a relevant silicon area and further they do not have a good noise rejection.
It would be desirable to have a sufficiently fast analog-to-digital conversion loop that may be embedded in PSI5 or WSS systems, that occupies a reduced silicon area and that has a good noise rejection.